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| AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. 2M x 32 FLASH FLASH MEMORY MODULE AVAILABLE AS MILITARY SPECIFICATIONS * Military Processing (MIL-STD-883C para 1.2.2) * Temperature Range -55C to 125C AS8F2M32 FLASH FIGURE 1: PIN ASSIGNMENT (Top View) 68 Lead CQFP FEATURES * Fast access times of 90ns, 120ns, and 150ns * 5.0V 10%, single power supply operation * Low power consumption(TYP): 4A CMOS stand-by * TYP ICC(active) <120mA for READ/WRITE * 20 year DATA RETENTION * Minimum 1,000,000 Program/Erase Cycles per sector guaranteed * 32 equal sectors of 64 Kbytes each * Any combination of Sectors can be Erased * Group Sector Protection * Supports FULL Chip Erase * Compatible with JEDEC standards * Embedded Erase and Program Algorithms * Data\ Polling and Toggle bits for detection of program or erase cycle completion. * Erase Suspend/Resume * Hardware Reset pin (RESET\) * Built in Decoupling Caps and Multiple Ground Pins for Low Noise Operation * Separate Power and Ground Planes to improve noise immunity GENERAL DESCRIPTION The Austin Semiconductor, Inc. AS8F2M32 is a 64 Mbit, 5.0 voltonly Flash memory. This device is designed to be programmed insystem with the standard system 5.0 volt VCC supply. The AS8F2M32 offers an access time of 90ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE\), write enable (WE\) and output enable (OE\) controls. The device requires only a single 5.0 volt power supply for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply FLASH standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-matching that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reaching data out of the device is similar to reading from other FLASH or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically time the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY\ pin, or by reading the DQ7 (DATA\ Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. (continued on page 2) Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. OPTION * Timing 90ns 120ns 150ns * Packages Ceramic Quad Flat Pack (0.88" sq) - MAX height .140" - Stand-off Height .035" min MARKING -90 -120 -150 Q For more products and information please visit our web site at www.austinsemiconductor.com AS8F2M32 Rev. 2.5 05/09 1 AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. GENERAL DESCRIPTION (cont.) The Sector Erase Architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware Data Protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The Hardware Sector Protection feature disables both program and erase operations in any combinations of the sectors of memory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for AS8F2M32 FLASH any period of time to read data form, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The Hardware RESET\ pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET\ pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the FLASH memory. The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. FIGURE 2: FUNCTIONAL BLOCK DIAGRAM WE 1\, CS1\ RESET\ OE\ A0 - A20 WE 2\, CS2\ WE 3\, CS3\ WE 4\, CS4\ 2M x 8 2M x 8 2M x 8 2M x 8 8 8 8 8 I/O0-7 I/O8-15 I/O16-23 I/O24-31 PIN DESCRIPTION PIN I/O0-31 A0-20 WE\1-4 CS\1-4 OE\ VCC GND RESET\ DESCRIPTION Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Power Supply Ground Reset AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* Voltage on any pin relative to VSS, VT**..............-2.0V to +7.0V Power Dissipation, PT...............................................................4W Storage Temperature, Tstg..................................-65C to +125C Short Circuit Output Current, IOS(1 output at a time)......100mA Endurance - Write/Erase Cycles ....................100,000 min cycles Data Retention...................................................................20 years AS8F2M32 FLASH *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow, and humidity (plastics). ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (4.5V < VCC < 5.5V , -55C < TA < +125C) DESCRIPTION Input Leakage Current Output Leakage Current VCC Active Current for Read VCC Active Current for Program or Erase VCC CMOS Standby VCC Standby Current Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage CONDITIONS VCC = 5.5, VIN = GND to V CC VCC = 5.5, VIN = GND to V CC CS\ = VIL, OE\ = V IH CS\ = VIL, OE\ = V IH VCC = 5.5V, All Inputs @ V CC - 0.2V or VSS +0.2V, RESET\ = CS\ 1-4 = VCC -0.2V VCC = 5.5, CS\ = V IH, RESET\ = V CC 0.3V, f=0 IOL = 12.0 mA, V CC = 4.5 IOH = -2.5 mA, V CC = 4.5 SYMBOL ILI ILOx32 ICC1 ICC2 ISB ICC3 VOL VOH VLKO 0.85 x VCC 3.2 4.2 MIN -10 -10 MAX 10 10 160 240 4 8 0.45 UNITS A A mA mA mA mA V V V PARAMETER Supply Voltage Ground Input High Voltage Input Low Voltage SYMBOL VCC VSS VIH VIL MIN 4.5 0 2.2 -0.5 TYP 5.0 0 ----- MAX 5.5 0 VCC + 0.5 +0.8 UNIT V V V V CAPACITANCE (TA = +25C)* PARAMETER OE\ WE\ 1-4 CS\1-4 Data I/O Address input SYM COE CWE CCS CI/O CAD VIN = 0V, f = 1.0 MHz CONDITIONS MAX 50 50 20 20 50 UNITS pF pF pF pF pF *Parameter is guaranteed, but not tested. AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. AS8F2M32 FLASH ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (VCC = 5.0V, -55C < TA < +125C) MIN WE\ CONTROLLED (WRITE/ERASE/PROGRAM OPERATIONS) Write Cycle Time Chip Select Setup Time Write Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Write Enable Pulse Width High Duration of Byte Progreamming Operation Sector Erase 2 1 PARAMETER SYM -90 MAX -120 MIN MAX 120 0 50 0 50 0 50 20 -150 UNITS MIN MAX 150 0 50 0 50 0 50 20 ns ns ns ns ns ns ns ns 300 15 0 50 s sec s s 44 256 10 500 150 sec sec ns ns ns 150 150 55 35 35 0 ns ns ns ns ns ns 20 150 0 50 0 50 0 50 20 s ns ns ns ns ns ns ns ns 300 15 0 s sec s 44 256 10 sec sec ns tAVAV tELWL tWLWH tAVWL tDVWH tWHDX tWLAX tWHWL tWHWH1 tWHWH2 tGHWL tVCS 3 tWC tCS tWP tAS tDS tDH tAH tWPH 90 0 45 0 45 0 45 20 300 15 0 50 44 256 300 15 0 50 44 256 10 500 120 Read Recovery Time before Write VCC Setup Time Chip Programming Time Chip Erase Time 4 5 Output Enable Hold Time RESET\ Pulse Width tOEH tRP tAVAV tAVQV tELQV tGLQV 6 6 10 500 90 90 90 40 20 20 0 20 READ-ONLY OPERATIONS Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Select High to Output High tRC tACC tCE tOE tDF tDF tOH 120 120 50 30 30 0 20 120 0 50 0 50 0 50 20 tEHQZ tGHQZ tAXQX Output Enable High to Output High Output Hold from Adresses, CS\ or OE\ Change, whichever is First 6 tReady RST Low to Read Mode CS\ CONTROLLED (WRITE/ERASE/PROGRAM OPERATIONS) Write Cycle Time Write Enable Setup Time Chip Select Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Chip Select Pulse Width High Duration of Byte Progreamming Operation Sector Erase Time 2 1 tAVAV tWLEL tELEH tAVEL tDVEH tEHDX tELAX tEHEL tWHWH1 tWHWH2 tGHEL 3 tWC tWS tCP tAS tDS tDH tAH tCPH 90 0 45 0 45 0 45 20 300 15 0 44 256 300 15 0 44 256 10 Read Recovery Time Chip Programming Time Chip Erase Time 4 5 Output Enable Hold Time tOEH 10 AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. NOTES: 1. 2. 3. 4. 5. 6. Typical value for tWHWH1 is 7s. Typical value for tWHWH2 is 1 sec. Typical value for Chip Programming is 14 sec. Typical value for Chip Erase Time is 32 sec. For Toggle an Data Polling. This parameter is guaranteed, but not tested. AS8F2M32 FLASH AC TEST CONDITIONS VIL = 0, VIH = 3.0 Input Rise and Fall 5 Input and Output Reference Level 1.5 Output Timing Reference Level 1.5 PARAMETER Input Pulse Levels TYP UNIT V ns V V FIGURE 3: AC TEST CURRENT FIGURE 4: RESET Timing Diagram AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. FIGURE 5: AC Waveforms for READ Operations AS8F2M32 FLASH FIGURE 6: WE\ Controlled, WRITE/ERASE/PROGRAM Operation NOTES: 1. 2. 3. 4. 5. PA is the address of the memory location to be programmed. PD is the data to be programmed at byte address. D7\ is the output of the complement of the data written to each chip. DOUT is the output of the data written to the device. Figure indicates last two bus cycles of four bus cycle sequence. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS8F2M32 Rev. 2.5 05/09 6 AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. FIGURE 7: AC Waveforms Chip/Sector ERASE Operations AS8F2M32 FLASH NOTES: 1. SA is the sector address for Sector ERASE. FIGURE 8: AC Waveforms for DATA\ Polling During Embedded Algorithm Operations AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. AS8F2M32 FLASH FIGURE 9: Alternate CS\ Controlled Programming Operation Timings NOTES: 1. 2. 3. 4. 5. PA is the address of the memory location to be programmed. PD is the data to be programmed at byte address. D7\ is the output of the complement of the data written to each chip. DOUT is the output of the data written to the device. Figure indicates last two bus cycles of four bus cycle sequence. AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. AS8F2M32 FLASH MECHANICAL DEFINITION ASI Case #703 (Package Designator QW) NOTES: 1. Dimensions are shown as millimeters(inches). AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. AS8F2M32 FLASH MECHANICAL DEFINITIONS* (Package Designator QT) AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10 AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. AS8F2M32 FLASH ORDERING INFORMATION EXAMPLE: AS8F2M32QW-120/XT Device Number AS8F2M32 AS8F2M32 AS8F2M32 Package Type QW QW QW Speed ns - 90 - 120 - 150 Process /* /* /* EXAMPLE: AS8F2M32QT-90/MIL Device Number AS8F2M32 AS8F2M32 AS8F2M32 Package Type Q Q Q Speed ns - 90 - 120 - 150 Process /* /* /* *AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Extended Temperature Range MIL = MIL-STD-883C para 1.2.2 Processing NOTE: QW package is planned future offering Temperature -40oC to +85oC -55oC to +125oC -55oC to +125oC AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 11 AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. DOCUMENT TITLE 64Mb, 2M x 32 Flash Memory Module REVISION HISTORY Rev # 2.5 History Updated Order Chart (QT to Q) Release Date May 2009 AS8F2M32 FLASH Status Release AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 12 |
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